Warning

This project is not complete.

Warning

This project is currently in to process of moving from a custom ISA to the RISC-V ISA and thus some of this documentation is for RISC-V ISA and some is not.

Welcome to KORE’s documentation!

Indices and tables

• Index

• Module Index

• Search Page

Module Documentation

• Keyboard
• Screen
• Terminal

KS++ Documentation

• 1. KS++ Specification Design Ideas

Virtual Mechine Documentation

• 1. Virtual Mechine Specification
• 2. Virtual Mechine Structural Elements

Assembly Documentation

• 1. Assembly Specification
  • 1.1. Data Types
  • 1.2. Registers and Stack
  • 1.3. Addressing Mode
  • 1.4. Instructions
• 2. Assembly Structural Elements

Instructions

• 1. Assembly Instruction Catalog
  • 1.1. Data Types
  • 1.2. Instructions

Machine Instruction Format (1s and 0s)

• 1. RISC V Data Format
  • 1.1. Instruction

Architecture Documentation

• 1. Architecture Design
  • 1.1. CPU Design
• 2. Architecture Structural Elements
  • 2.1. Map of Registers